Frequency trimming is provided by the potentiometer  on the PCB which puts unlocked/undisciplined operation close to 125.0000 MHz.  When an external 125 MHz reference signal of -15 to +15 dBm is injected at the SMA, the PLL "turns on" to phase lock the VCXO to the external reference. It is also possible to use a 1/5th frequency, 25 MHz, external reference with reduced capture range. Measured spectral noise power density is more than adequate for any HF communications from FST4W to >10 kHz information bandwidths. The external input terminal is DC blocked and completely isolated to greatly reduce common mode currents.  It presents 50 ohm impedance to the driving external reference so that when normal 50 ohm coaxial cable is  used the shape of the reference signal is maintained.

I don't have a Red Pitaya to demonstrate it on but circuits are essentially identical so I would expect identical performance.   This should also work to provide GNSS or local OCXO/Rubidium frequency referencing for QDX (25 MHz VCXO) and other radios as well simply by selecting an appropriate VCXO. Quite a variety of frequencies and output types, PECL, LVDS and CMOS to accommodate a variety of SDR clocks seem to be available at quite low prices. Renesas offers > 900 varieties with different Vcc and output types available at many common frequencies.

Here's a measurement made with the PCB lying on the bench, with leads strewn around without lock (cyan) and with external 125 MHz GNSS disciplining (yellow). One  can see the ~3 kHz PLL bandwidth cleaning up some low level mains related spurs present on the unlocked VCXO (blue).