Microprocessor Cache-Coherency Snooping

The term "snooping" commonly refers to at least three different actions, only two of which are supported by the AMD-K5 and Pentium™ processors:

Inquire Cycles: These are bus cycles, initiated by external logic, that cause the processor to look up an address in its physical cache tags. Both the AMD-K5 and Pentium processors support inquire cycles.
Internal Snooping: These are internal actions by the processor (rather than external logic) that are taken during certain types of cache accesses in order to detect self-modifying code. Both the AMD-K5 and Pentium processors support internal snooping.
Bus Watching: Some caching devices watch their address and data bus continuously while they are held off the bus, comparing every address driven by another bus master with their internal cache tags and optionally updating their cached lines on the fly, during writebacks by the other master. Neither the AMD-K5 nor the Pentium processor supports bus watching.

The table below shows the conditions under which snooping occurs in the AMD-K5 processor and the resources that are snooped. All such snooping is done in the processor's physical tags, in parallel with the processor's own accesses to the linear tags. Thus, there is no execution-performance penalty for snooping.

Origin of Snoop	Type of Access		Snooping Action
			Instructions			Data
			Instruction Cache	Prefetch Buffer	Line-Fill Buffer	Data Cache	Store Buffer	Writeback Buffers
External	Inquire Cycle		yes¹	no	no	yes¹	no	yes¹
Internal	Instruction Cache	Read Miss	n.a.	n.a.	n.a.	yes²	yes²	yes²
	Instruction Cache	Read Hit	n.a.	n.a.	n.a.	no	no	no
	Data Cache	Read Miss	yes³	yes³	yes³	n.a.	n.a.	n.a.
		Read Hit	no	no	no	n.a.	n.a.	n.a.
		Write Miss	yes⁴	yes⁴	yes⁴	n.a.	n.a.	n.a.
		Write Hit	no	no	no	n.a.	n.a.	n.a.
1. The processor's response to a snoop hit depends on the state of the INV input signal and the state of the cache line. If INV is negated, the line remains in or transitions to the shared state. If INV is asserted, the line is written back, if modified in the data cache, and then invalidated. 2. If the snoop hits a line in the data cache, store buffer or writeback buffer, the line is written back (if modified) and invalidated. Then, the instruction-cache read is performed again. If the line is modified, a copy of the writeback data is passed directly to the instruction cache, thus avoiding a line-fill bus cycle after the writeback bus cycle. 3. If the snoop hits a line in the instruction cache, prefetch buffer, or line-fill buffer, the line stays valid and the data-cache read is performed again, but as a single, non-cacheable read. 4. If the snoop hits a line in the instruction cache, prefetch buffer, or line-fill buffer, the line is invalidated and the data-cache write is performed. n.a. = not applicable

Inquire Cycles

In systems with multiple caching masters, external logic maintains cache coherency by driving inquire cycles to the processor. System logic initiates inquire cycles by asserting AHOLD, BOFF#, or HOLD to obtain control of the address bus, and then driving EADS#, INV and an inquire address. Such bus cycles cause the processor to compare the physical tags for both its instruction and data caches with the inquire address. If the compare hits a shared or exclusive line in the data cache or a valid line in the instruction cache, the processor asserts HIT#. If the compare hits a modified line in the data cache, the processor asserts HITM#.

The resulting state of a cache line that is hit depends on the state of the INV signal at the time of the inquire cycle. If INV is negated, the line remains in or transitions to the shared (or valid) state. If INV is asserted, the line is written back, if modified in the data cache, and then invalidated.

Internal Snooping

The processor automatically snoops its instruction cache during read or write misses to its data cache, and it snoops its data cache during read misses to its instruction cache. It does this to detect the presence of self-modifying code. If an internal snoop hits its target, the processor does the following:

During Instruction-Cache Read Miss: The line in the data cache, store buffer or writeback buffer is written back (if modified) and invalidated, and the instruction-cache read is performed again. If the data-cache line was modified, a copy of the writeback data is passed directly to the instruction cache, thus avoiding a line-fill bus cycle after the writeback bus cycle.
During Data-Cache Read Miss: The line in the instruction cache, prefetch buffer, or line-fill buffer stays valid, and the data-cache read is performed as a single, non-cacheable read.
During Data-Cache Write Miss: The line in the instruction cache, prefetch buffer, or line-fill buffer is invalidated, the reorder buffer invalidates all instructions in the pipeline following the instruction that initiated the snoop, and the data-cache write is performed.

The AMD-K5 processor, like the 486 processor but unlike the Pentium processor, requires a jump (near or far) after a self-modifying write to clear the prefetch buffer. However, both the AMD-K5 and the Pentium processors require a serializing instruction after self-modifying code whose physical address is aliased to multiple linear addresses.