Cisco Memoir 2R1W Memory IP Core for SRAM Datasheet

A datasheet describing an SRAM memory IP core that wraps around standard IBM one-port SRAM1D macros to support two-port functionality. The core appears to the user as a full-featured two-port read-write memory block with a simple, pipelined SRAM interface.

• Length: 10 pages
• Audience: Memory system designers
• Service Performed: Editing, figures, and formatting